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applications avionics data communication serial to parallel conversion parallel to serial conversion hi-8683, hi-8684 arinc interface device arinc 429 & 561 serial data to 8-bit parallel data description the hi-8683 and hi-8684 are system components for interfacing incoming arinc 429 signals to 8-bit parallel data using proven +5v analog/digital cmos technology. the hi-8683 is a digital device that requires an external analog line receiver such as the hi-8482 or hi-8588 between the arinc bus and the device inputs. the hi-8684 incorporates the digital logic and analog line receiver circuitry in a single device. the hi-8683 is also available as a second source to the dls-112 18 pin dip and 28 pin plcc package pinouts. the receivers on the hi-8684 connect directly to the arinc 429 bus and translate the incoming signals to normal cmos levels. internal comparator levels are set just below the standard 6.5 volt minimum data threshold and just above the standard 2.5 volt maximum null threshold. the -10 version of the hi-8684 allows the incorporation of an external 10k resistance in series with each arinc input for lightning protection without affecting arinc level detection. both products offer high speed 8-bit parallel bus interface, a 32-bit buffer, and error detection for word length and parity. a reset pin is also provided for power-on initialization. with the original automatic conversion of serial arinc 429, 575 & 561 data to 8-bit parallel data high speed parallel 8-bit data bus error detection - and on-chip line receiver option (hi-8684) input hysteresis of at least 2 volts (hi-8684) test inputs bypass analog inputs (hi-8684) simplified lightning protection with the ability to add 10 kohm external series resistors (hi-8684-10) plastic package options - surface mount (soic), plcc and dip industrial and extended temperature ranges word length parity reset input for power-on initialization features pin configurations (top view) october 2008 datardy d7 d6 d5 d4 d3 d2 d1 d0 hi-8684psi hi-8684pst & hi-8684psi-10 hi-8684pst-10 1 2 3 4 5 6 7 8 9 10 (see page 8 for additional pin configurations) 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 20 19 18 17 16 15 14 13 12 11 hi-8683 18-pin plastic soic - wb package hi-8684 20-pin plastic soic - wb package hi-8683psi hi-8683pst vcc gapclk inb ina error parity enb gnd reset read gapclk testa testb rinb (-10) rina (-10) error parity enb gnd reset read vcc datardy d7 d6 d5 d4 d3 d2 d1 d0 (ds8683 rev. j) 10/08 holt integrated circuits www.holtic.com
data rdy output receiver data ready flag. a high level indicates data is available in the receive buffer. flag goes low when the first 8-bit byte is read. d0 to d7 output 8-bit parallel data bus (tri-state) gnd power 0v input read strobe. a low level transfers receive buffer data to the data bus parity enb input parity enable - a high level activates odd parity checking which replaces the 32nd arinc bit with an error bit. otherwise, the 32nd arinc bit is unchanged error output error flag. a high level indicates a bit count error (number of arinc bits was less than or greater than 32) and/or a parity error if parity detection was enabled (parity enb high) ina input positive digital serial data input (hi-8683 only) inb input negative digital serial data input (hi-8683 only) rina/rina-10 input positive direct arinc serial data input rinb/rinb-10 input negative direct arinc serial data input (hi-8684 & hi-8684-10 only) input internal logic states are initialized with a low level testa input used in conjunction with the testb input to bypass the built-in analog line receiver circuitry testb input u gapclk input gap clock. determines the minimum time required between arinc words for detection. the minimum word gap time is between 16 and 17 clock cycles of this signal. vcc power +5v 5% supply signal function description read reset (hi-8684 & hi-8684-10 only) (hi-8684 & hi-8684-10 only) sed in conjunction with the testa input to bypass the built-in analog line receiver circuitry (hi-8684 & hi-8684-10 only) hi-8683, hi-8684 pin descriptions functional description the hi-8683 and hi-8684 are serial to 8-bit parallel convert- ers. the incoming data stream is serially shifted into an input register, checked for errors, and then transferred in parallel to a 32-bit receive buffer. the receive data can be accessed us- ing four 8-bit parallel read operations while the next serial data steam is being received. figure 1 is a block diagram of both the hi-8683 and hi-8684. the difference between the two products is the hi-8684 has a built-in line receiver whereas the hi-8683 is strictly a digital device and requires an external arinc line receiver such as the holt hi-8444, hi-8445, hi-8448 , hi-8482 or hi-8588 to in- terface to the arinc 429 bus. receiver inputs hi-8684 line receiver internal 35k resistors are in series with both the rina and rinb arinc 429 inputs. they connect to level translators whose resistance to gnd is typically 10k after level trans- lation, the buffered inputs drive a differential amplifier. the differential signal is compared to levels derived from a divider between vcc and gnd. the nominal settings correspond to a one/zero amplitude of 6.0v and a null amplitude of 3.3v. a valid arinc one/zero input sets a latch and a null input re- sets the latch. since any added external series resistance will affect the volt- age translation, the hi-8684-10 is available with 25k of the 35k series resistance required for proper arinc 429 level detection. the remaining 10k required that must be added can be incorporated in other external circuitry such as light- ning protection. except for the different input series resis- tance, the hi-8684 and hi-8684-10 are identical. holt integrated circuits 2
protocol detection arinc clock and data in the hi-8683 are derived from the two streams of digital data at the ina and inb inputs and the resulting one/zero data is shifted into a 32-bit input register as illustrated in figure 3. in the hi-8684, the one/zero data shifted into the input reg- ister is created from either the two digital outputs of the built- in line receiver (figure 3) or the testa and testb inputs (figure 4). for arinc 561 operation, the ina and inb data streams in- puts must be derived from the arinc 561 data, clock and sync with external logic. gap detection the end of a data word is detected by an internal counter that times out when a data one or zero is not received for a period equal to 16 cycles of the gapclk signal. the gap detection time may vary between 16 and 17 cycles of the gapclk signal since the incoming data and gapclk are not usually synchronous inputs. the required frequency of gapclk is a function of the mininum gap time specified for the type of arinc data being received. table 1 indicates typical frequencies that may be used for the various data rates normally encountered. figure 1. block diagram databus bit period minimum gap gap clock gap detection type ( s) (s) mhz time (s) 429 10 45 0.75 21.3 - 22.7 1.0 16 - 17 1.5 10.7 - 11.3 429 69 - 133 310 - 599 0.1 160 - 170 575 69 - 133 310 - 599 0.1 160 - 170 561 69 - 133 103 - 200 0.2 80 - 85 table1-t ypical gap detection times functional description (cont.) bit count parity detect gap detect 32-bit shift reg. 32-bit receive buffer 32-bit to 8-bit mux error detect clock & data detect hi-8683 only hi-8684 only ina parity enb inb rinb testa testb gapclk reset byte count read data rdy error 32 8 32 esd protection & line receiver esd protection rxa rxb 10k bit 32 bit 32 rina d0-d7 data clk rinb-10 rina-10 10k 25k 25k hi-8683, hi-8684 holt integrated circuits 3
hi-8683, hi-8684 error checking reading receive buffer once a word gap is detected, the data word in the input reg- ister is transferred to the receive buffer and checked for er- rors. when parity detection is enabled (parity enb high), the received word is checked for odd parity. if there is a parity error, the 32nd bit of the received data word is set high. if parity checking is disabled (parity enb low) the 32nd bit of the data word is always the 32nd arinc bit received. the error flag output is set high upon receipt of a word gap and the number of bits received since the previous word gap is less than or greater than 32. the error flag is reset low when the next valid arinc word is written into the receive buffer or when is pulsed low. when the data word is transferred to the receive buffer, the data rdy pin goes high. the data word can then be read in four 8-bit bytes by pulsing the input low as indi- cated in figure 5. the first read cycle resets data rdy low and increments an internal counter to the next 8-bit byte. the counter continues to increment on each read cy- cle until all four bytes are read. the relationship between each bit of an arinc word received and each bit of the four 8-bit data bus bytes is specified in figure 2. when a new arinc word is received it always overwrites the receive buffer. if the first byte of the previous word has not been read, then previous data is lost and the receive buffer will contain the new arinc word. however, if the data rdy pin goes high between the reading of the first and fourth bytes, the previous read bytes are no longer valid because the unread bytes have been overwritten by the new arinc word. also, the next read will be of the first byte of the new arinc word since the internal byte counter is always reset to the first byte when new data is trans- ferred to the receive buffer. reset read functional description (cont.) -1.50 to +1.50v -1.50v to +1.50v 0 0 0 0 -3.25v to -6.50v +3.25v to +6.50v 0 0 0 1 +3.25v to +6.50v -3.25v to -6.50v 0 0 1 0 x x 0101 x x 1010 x x 1100 x = don't care rina rinb testa testb rxa rxb truth table 1 read byte data bus bits arinc bits 1st byte 1 d0 - d7 arinc 1 - arinc 8 2nd byte 2 d0 - d7 arinc 9 - arinc 16 3rd byte 3 d0 - d7 arinc 17 - arinc 24 4th byte 4 d0 - d7 arinc 25 - arinc 32 figure 2. order of received data reset test mode (hi-8684 only) a low on the input sets a flip-flop which initializes the internal logic. when goes high, the internal logic remains in the initialized state until the first word gap is detected preventing reception of a partial word. the built-in differential line receiver on the hi-8684 can be disabled allowing the data and clock detection circuitry to be driven directly with digital signals. the logical or func- tion of the testa and testb is defined in truth table 1. the two inputs can be used for testing the receiver logic and for inputting arinc 429 type data derived from another source / protocol. see figure 4 for typical test input timing. the device should always be initialized with imme- diately after entering the test mode to clear a partial word that may have been received since the last word gap. oth- erwise, an error condition may occur and the first 32 bits of data on the test inputs may not be properly re- ceived. also, when entering the test mode, both testa and testb should be set high and held in that state for at least one word gap period (17 gap clocks) after goes high. when exiting the test mode, both test inputs should be held low and the device initialized with reset reset reset reset reset. holt integrated circuits 4
hi-8683, hi-8684 testa +5v 0v testb 0v +5v derived clock derived data derived clock arinc data bits word gap 28 29 30 31 32 1 2 4 bit periods min. ina (hi-8683 only) inb (hi-8683 only) vdiff rina - rinb (hi-8684 only) derived data 0v 0v +5v 0v +10v +5v -10v timing diagrams figur e 3 - receiver input timing for arinc 429 figur e 5 - receiver parallel databus timing data rdy read d0-d7 valid t rdyclr t rdpw t rr t fd t rd valid valid valid 1st 8-bits 2nd 8-bits 3rd 8-bits 4th 8-bits t drdy derived data 32nd arinc bit figur e 4 - test input timing for arinc 429 arinc data bits word gap 28 29 30 31 32 1 2 4 bit periods min. holt integrated circuits 5
supply voltages v ...................................................+5v temperature range industrial ................................ -40c to +85c hi-temp ............................... -55c to +125c junction temperature, tj ................... +175c cc 5% parameters symbol test conditions min typ max units arinc bus inputs digital inputs (rina & rinb, hi-8684 only) differential input voltage one or zero v differential voltage 6.5 10.0 13.0 volts null v " " " " - - 2.75 volts common mode v with respect to gnd - - 5.0 volts input resistance rina (-10) to rinb (-10) r supplies floating 30 75 - kohm rina (-10) or rinb (-10) to gnd or v r " " " ' 19 40 - kohm input capacitance (guaranteed but not tested) differential c rina to rinb - - 20 pf to gnd c - - 20 pf to v c - - 20 pf (ina, inb, , gapclk, & parity enb) input voltage high v 2.0 - v volts low v 0.0 - 0.8 volts input current source i v = 5.0v - - 1.0 a sink i v = 0.0v -1.0 - - a input capacitance c - - 8.0 pf din nin com diff cc sup diff g cc h ih cc il ih in il in i reset read all voltages referenced to gnd supply voltages v ....................................................... +7.0v voltage on inputs rina (-10) to rinb (-10) ......... +29v to - 29v all other input pins..................-0.3 to vcc +0.3 dc current per input pin ....................... +10ma power dissipation at 25c plastic 18-pin so..... 1.9w, derate 15.4mw/c plastic 18-pin dip .....1.6 plastic 20-pin so ......1.4 plastic 20-pin plcc .2.0 solder temperature leads ................................ +280c for 10 sec package body .....................................+220c storage temperature ............. -65c to +150c cc w, derate 13.3mw/c w, derate 11.5mw/c w, derate 17.2mw/c note: stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device. these are stress ratings only. operation at the limits is not recommended. absolute maximum ratings recommended operating conditions vcc = 5v, gnd = 0v, ta = operating temperature range (unless otherwise specified). dc electrical characteristics hi-8683, hi-8684 holt integrated circuits 6
vcc = 5v, gnd = 0v, ta = operating temperature range (unless otherwise specified). hi-8683, hi-8684 dc electrical characteristics (cont.) parameters symbol test conditions min typ max units digital inputs outputs operating supply current (testa & testb) input voltage high v 2.4 - v low v 0.0 - 0.8 volts input current source -110 - sink -1.0 - - input capacitance c - - 8.0 pf (d0 to d7, error & data rdy) output voltage high low i = 1.6 ma - - 0.4 volts output tri-state current (d0 - d7 only) v = 5.0v - - 1.0 a v = 0.0v -1.0 - - output capacitance - - 15 pf v (hi-8683 only) i v = 0.0v, outputs open - - 1.0 m v (hi-8684 only) i v = 0.0v, outputs open - - 6.5 m ih cc il i ol oh ol cc cc1 in cc cc2 in volts i v = 5.0v a i v = 0.0v a v i = -1.0 ma 2.7 - - volts v i ia c a a ih in il in oh oh ol ih il o parameters symbol test conditions min typ max units pulse width t 50 ns data delay from t 40 ns to data floating t 20 ns to data rdy clear t 35 ns pulse to next pulse t 25 ns gapclk frequency f 1 mhz 32 arinc bit to data rdy t 16 17 clocks read read read read read read rdpw rd fd rdyclr rr gc drdy ac electrical characteristics vcc = 5v, gnd = 0v, ta = operating temperature range (unless otherwise specified). holt integrated circuits 7
3-d7 2-datardy 1--v 20 - gapclk 19 - testa cc hi-8684pji hi-8684pjt & hi-8684pji-10 hi-8684pjt-10 18 - testb 17 - 16 - rinb (-10) 15 - rina (-10) 14 - error reset d6-4 d5-5 d4-6 d3-7 d2-8 vcc gapclk inb ina error parity enb d0 reset read data rdy d6 d7 d5 d4 d3 d2 d1 gnd 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 hi-8683pdi hi-8683pdt 3-d7 2-datardy 1--v 20 - gapclk 19 - n/a cc hi-8683pji hi-8683pjt 18 - n/a 17 - 16 - inb 15 - ina 14 - error reset d6-4 d5-5 d4-6 d3-7 d2-8 d1 - 9 d0-10 gnd-1 1 -12 parity - 13 enb read hi-8683, hi-8684 hi-8683 & hi-8684 pin configurations (see page 1 for additional pin configurations) d1 - 9 d0-10 gnd-1 1 -12 parity - 13 enb read hi-8683 20-pin plastic plcc hi-8684 20-pin plastic plcc hi-8683 18-pin plastic dip ordering information legend: wb - wide body (1): only available with ?hi-8684? hi - 868xxx x - xx x package description built-in line recv?r 20 pin plastic plcc (20j) 20 pin plastic plcc (20j) no yes 18 pin plastic dip (18p) no part number 8683pj 8684pj 8683pd 18 pin plastic wide soic (18hw) 20 pin plastic wide soic (20hw) no yes 8683ps 8684ps temperature range flow burn in -40c to +85c no i -55c to +125c no t part number t i lead finish part number 100% matte tin (pb-free, rohs compliant) f tin / lead (sn / pb) solder blank input series resistance built-in required externally part number (1) 25 kohm 10 kohm -10 35 kohm 0 no dash number holt integrated circuits 8
revision history hi-8683, hi-8684 revision date description of change ds8683, rev. j 10/15/08 removed character shadow on some of the 18-pin pdip dimensions and clarified temperature ranges. holt integrated circuits 9
.905 .015 (22.99 .381) .300 .010 (7.62 .254) .135 .015 (3.429 .381) (4.064 .250 .010 (6.350 .254) 7 typ. .160 .025 .635) .130 .020 (3.302 .508) .019 .004 (.483 .102) .055 .010 (1.397 .254) .100 bsc (2.54) .335 .035 (8.509 .889) .0115 .0035 (.2921 .0889) hi-8683, hi-8684 package dimensions 18-pin plastic dip inches (millimeters) package type: 18p bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) 18-pin plastic small outline (soic) - wb (wide body) inches (millimeters) package type: 18hw bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) .454 .008 (11.531 .20) .4065 .0125 (10.325 .32) .292 .005 (7.417 .13) 0 to 8 .033 .017 (.838 .43) .090 .010 (2.286 .254) .0075 .0035 (.191 .089) .0105 .0015 (.2667 .038 .050 (1.27) bsc see detail a detail a .0165 .003 (.419 .09) holt integrated circuits 10
hi-8683, hi-8684 package dimensions 20-pin plastic small outline (soic) - wb (wide body) inches (millimeters) package type: 20hw bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) .5035 .0075 (12.789 .191) .4065 .0125 (10.325 .318) .295 .002 (7.493 .051) 0 to 8 .090 .010 (2.286 .254) .0075 .0035 (.191 .089) .018 (.457) typ see detail a detail a .033 .017 (.838 .432) .0105 .0015 (.2667 .0381) .050 (1.27) bsc 20-pin plastic plcc inches (millimeters) package type: 20j pin no. 1 ident .045 x 45 .353 .003 (8.966 .076) sq. .017 .004 (.432 .102) .390 .005 (9.906 .127) sq. .173 .008 (4.394 .203) . 310 .020 (7.874 .508 ) .049 x 45 .050 (1.27) bsc see detail a detail a .035 .889 r .010 .001 (.254 .03) .020 (.508) min bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) holt integrated circuits 11

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